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Communication Dans Un Congrès Année : 2009

Low Power Multistandard Simultaneous Reception Architecture

Résumé

In this paper, we address the architecture of multistandard simultaneous reception receivers and we aim at improving both the complexity and the power consumption of the analog front-end. To this end we propose an architecture using the double orthogonal translation technique in order to multiplex two received signals. A study case concerning the simultaneous reception of 802.11g and UMTS signals is developed in this article.
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Dates et versions

inria-00412028 , version 1 (27-11-2009)

Identifiants

  • HAL Id : inria-00412028 , version 1

Citer

Ioan Burciu, Jacques Verdier, Guillaume Villemaud. Low Power Multistandard Simultaneous Reception Architecture. European Wireless Technology Conference 2009, Sep 2009, Rome, Italy. ⟨inria-00412028⟩
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